THE QUICK TAKE
  • Developer Divyansh Agrawal claims he embedded a 32-bit RISC-V processor directly into Qwen3.5-4B's weight layers — with zero learned weights, according to the developer.
  • Agrawal says the system executed 18 million instructions without an error, but no independent researcher has publicly confirmed that figure or reproduced the result.
  • The developer reports benchmark scores of 97.5–100% on DeepMind arithmetic tasks, though community observers question whether the project has practical value beyond a clever demo.

What Folks Are Hollerin' About

Well, butter my biscuit — word around the digital holler is that a solo developer going by Divyansh Agrawal has done something that sounds about as plausible as a catfish climbing a pine tree. According to Agrawal's personal blog at divagr.com, he has taken Qwen3.5-4B, a large language model, and — the developer says — compiled a fully functioning, deterministic 32-bit RISC-V processor smack into its weight layers. The project, which the developer calls Qwenputer, has been generating considerable buzz on Hacker News, X, and developer watering holes like daily.dev, though the excitement itself is not evidence that any of this works the way the developer claims.

The developer describes the result as a hybrid model that can execute C and MicroPython code entirely during its own forward passes — no external runtime, no tool sandbox, no smoke and mirrors from outside the model, according to the developer. Agrawal published the checkpoint on Hugging Face and the code on GitHub, which means anyone with a 24 GB GPU and a free weekend could theoretically kick the tires. But as of this writing, no independent researcher has publicly confirmed the claims or reproduced the benchmark figures, so we are still squarely in 'one fella's word for it' territory.

What the Developer Actually Says He Built

According to Agrawal's blog, the processor is described as implementing the RV32IM instruction set plus the Zba extension and a bignum unit — the developer's own characterization of the architecture. The developer says the CPU occupies 11 transformer layers placed in front of Qwen's native 32 layers. Crucially, Agrawal claims none of those 11 layers contain learned weights: every weight value is computed by a compiler rather than trained by gradient descent. That is one heck of a claim, like saying you didn't grow the tomatoes — you just mathed them into existence.

The developer says the trick that makes addressable memory possible involves exploiting Qwen3.5's Gated DeltaNet attention layers, which appear in three out of every four attention positions. According to Agrawal, by setting the forget gate and write strength each to 1 and using one-hot key encoding, individual memory rows can be overwritten and read back exactly, while the recurrent state stays a fixed size regardless of how long the conversation gets. The developer additionally describes an in-model filesystem stored in that same DeltaNet state, which he says persists across conversations when the state is saved and reloaded — claiming roughly 90% recall of changed facts compared with around 30% when old chats were simply pasted back as context, though that figure is unverified.

Agrawal also says the checkpoint weighs in at 18.8 GB — about double the base model — and requires a small custom driver he calls RvChat to load firmware and keep execution trace tokens isolated. The developer is explicit that it cannot run with a plain generate() call, which is about as convenient as needing a special wrench to start your truck.

The Numbers the Developer Is Throwing Around

On the benchmark side, Agrawal reports some eye-popping figures — all of which, we must holler loudly, come exclusively from the developer's own testing with no third-party confirmation. According to the developer's reported results, Qwenputer scored between 97.5% and 100% on DeepMind arithmetic tasks, compared with 55% to 90% for the base Qwen3.5-4B model and 95% to 100% for the base model when given access to an external Python tool. On the NUPA long-integer benchmark, the developer claims Qwenputer hit 100% while the base model managed only 48.6%.

The developer also claims the system ran 18 million instructions free-running without a single error in his own testing, and says the implementation passes official riscv-tests suite checks with output matching QEMU — a standard reference emulator. Those are remarkable assertions. Remarkable assertions require more than one guy's blog post to graduate from 'interesting claim' to 'established fact,' and right now they have not made that trip.

What Is Genuinely Not Known

Here is where we slow the pickup down to a crawl. No independent researcher, academic institution, or established technology outlet has verified the benchmark numbers, confirmed the RISC-V test-suite results, or peer-reviewed the architectural claims made by the developer. The coverage from Adafruit's blog and daily.dev is based entirely on Agrawal's own writeup and his X thread — those outlets are amplifying the story, not verifying it. Hacker News community interest tells us people find this interesting, not that the claims are correct.

The project is open-source and the checkpoint is publicly available on Hugging Face, which in principle hands anyone the tools to independently validate the work. That is genuinely more than most extraordinary claims offer. But 'could be checked' and 'has been checked' are different things, and the gap between them is exactly where this story currently lives. Until someone outside the project publishes a reproduction, every figure in this article should be treated as Agrawal's reported claim, full stop.

Analysis: Why Anyone Gives a Hoot

This next part is analysis, not reporting — consider yourself warned, like a sign on a fence about an electric wire. If the claims hold up under independent scrutiny, the architectural idea is genuinely interesting for reasons that go beyond cleverness for its own sake. Using a recurrent attention mechanism as deterministic addressable RAM — rather than as a probabilistic language-modeling tool — would represent a meaningful expansion of what transformer-adjacent architectures can be conscripted into doing. The notion that you could compile, rather than train, weights to implement exact logic is the kind of thing that makes researchers sit up straight.

Community observers on daily.dev noted that commenters are simultaneously fascinated by the DeltaNet-as-RAM trick and skeptical about whether the project offers anything practically useful beyond being a very shiny demo. The developer frames Qwenputer as a proof-of-concept for what he describes as compiled-weight architectures, and suggests it could point toward in-model oversight and auditing tools — but that framing is the developer's own vision for the work, not an independently assessed conclusion. Also worth filing under 'acknowledged limitations': Agrawal's own blog notes that every instruction costs several decoded tokens, meaning large calculations take seconds. That is slower than a three-legged dog in a molasses flood, which matters a great deal if anyone ever wants to use this thing for something beyond impressing strangers on the internet.

Bottom Line from the Back Porch

What we have here is one developer, one blog post, one GitHub repo, one Hugging Face checkpoint, and a whole lot of community excitement — which is a fun combination but not a verified one. Agrawal's claimed architecture is creative enough that it deserves serious technical scrutiny, and the open availability of the code means that scrutiny is genuinely possible. But until independent researchers put it through its paces and publish what they find, the correct posture is enthusiastic curiosity paired with a healthy skepticism, like admiring a man's fish story while you wait to see the fish.

Who is doing the hollering

These links show where the chatter came from. A link is attribution, not our endorsement or independent confirmation.

  1. Qwenputer: a fully functioning, deterministic RISC-V CPU inside Qwen3.5Divyansh Agrawal (divagr.com) · primary
  2. GitHub - divagr18/qwenputerGitHub (divagr18) · primary
  3. divagr1925/Qwen3.5-4B-QwenputerHugging Face (divagr1925) · primary
  4. div (fp32) on X — Qwenputer announcement threadX (divagr1925) · social signal
  5. Qwenputer, a RISC-V CPU inside a model's weightsAdafruit Industries Blog · specialist
  6. Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5daily.dev · specialist
Revision record

Last checked Oct 29, 2026, 5:07 AM EDT. Talk Around Town: All technical claims — including benchmark scores, error-free instruction counts, and architectural descriptions — originate solely from the project's creator. Independent verification has not yet been published. Treat performance figures and architectural assertions as attributed claims, not established facts.